1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a boost voltage generating circuit for a nonvolatile ferroelectric memory device and method of generating a boost voltage. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for operating a nonvolatile ferroelectric memory device at a low voltage.
2. Discussion of the Related Art
Generally, a nonvolatile ferroelectric memory (i.e., a ferroelectric random access memory (FRAM)) has a data processing speed substantially the same as a dynamic random access memory (DRAM) and is able to retain data even in power off. For this reason, the nonvolatile ferroelectric memory has received much attention as a next generation memory device.
The FRAM and the DRAM are memory devices having similar structures. The FRAM, however, includes a ferroelectric capacitor having a high residual polarization characteristic. The residual polarization characteristic permits data to be maintained even if an electric field is removed.
FIG. 1 shows a hysteresis loop of a typical ferroelectric. As shown in FIG. 1, even if a polarization induced by the electric field has the electric field removed, data is maintained at a certain amount (i.e., xe2x80x9cdxe2x80x9d and xe2x80x9caxe2x80x9d states in FIG. 1) due to the presence of the residual polarization (or spontaneous polarization). A nonvolatile ferroelectric memory device utilizes the xe2x80x9cdxe2x80x9d and xe2x80x9caxe2x80x9d states corresponding to xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d, respectively.
A related art nonvolatile ferroelectric memory device will now be described. FIG. 2 shows a unit cell of a related art nonvolatile ferroelectric memory.
As shown in FIG. 2, the related art nonvolatile ferroelectric memory includes a bitline B/L formed in one direction, a wordline W/L formed to cross the bitline, a plate line P/L spaced apart from the wordline in the same direction as the wordline, a transistor Ti with a gate connected to the wordline and a source connected to the bitline, and a ferroelectric capacitor FC1. A first terminal of the ferroelectric capacitor FC1 is connected to a drain of the transistor T1 and a second terminal is connected to the plate line P/L.
Data input/output operation of the related art nonvolatile ferroelectric memory deviceandwill now be described as follows. FIG. 3A is a timing chart illustrating operation of a write mode of the related art nonvolatile ferroelectric memory device, while FIG. 3B is a timing chart illustrating operation of a read mode thereof.
During the write mode, an externally applied chip enable signal CSBpad is activated from high state to low state. At the same time, if a write enable signal WEBpad is applied from high state to low state, the write mode starts. Subsequently, if an address decoding in the write mode starts, a pulse applied to the corresponding wordline is transited from low state to high state to select a cell.
High and low signals in a certain period are sequentially applied to the corresponding plate line in a period where the wordline is maintained at high state. To write a logic value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d in the selected cell, a high signal or low signal synchronized with the write enable signal WEBpad is applied to the corresponding bitline.
In other words, if a high signal is applied to the bitline and the low signal is applied to the plate line in a period where the signal applied to the wordline is High, a logic value xe2x80x9c1xe2x80x9d is written in the ferroelectric capacitor. Conversely, if a low signal is applied to the bitline and the signal applied to the plate line is high, a logic value xe2x80x9c0xe2x80x9d is written in the ferroelectric capacitor.
Reading operation of data stored in a cell by the above the write mode operation will now be described as follows. If an externally applied chip enable signal CSBpad is activated from high state to low state, all of the bitlines become equipotential to a low voltage by an equalizer signal EQ before the corresponding wordline is selected.
Then, the respective bitline becomes inactive and an address is decoded. The low signal is transited to the high signal in the corresponding wordline according to the decoded address so that the corresponding cell is selected.
The high signal is applied to the plate line of the selected cell to destroy the data corresponding to the logic value xe2x80x9c1xe2x80x9d stored in the ferroelectric memory. If the logic value xe2x80x9c0xe2x80x9d is stored in the ferroelectric memory, the corresponding data is not destroyed.
The destroyed data and the undestroyed data are output as different values shown in the ferroelectric hysteresis loop, so that a sensing amplifier senses the logic value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d, respectively. In other words, if the data is destroyed, the xe2x80x9cdxe2x80x9d state is transited to the xe2x80x9cfxe2x80x9d state, as shown in the hysteresis loop of FIG. 1. If the data is not destroyed, the xe2x80x9caxe2x80x9d state is transited to the xe2x80x9cfxe2x80x9d state. Thus, if the sensing amplifier is enabled after a set time has elapsed, the logic value xe2x80x9c1xe2x80x9d is output in case that the data is destroyed while the logic value xe2x80x9c0xe2x80x9d is output in case that the data is not destroyed.
As described above, after the sensing amplifier outputs the data to recover the original data, the plate line becomes inactive from high state to low state at the state that the high signal is applied to the corresponding wordline.
When the data reading/writing operation is executed, a boost voltage can be generated in the wordline by using an NMOS capacitor (not shown).
However, the related art nonvolatile ferroelectric memory device has several problems as follows.
Since a boost voltage is not used when the cell is read and written, an error operation may occur in a low voltage region. Also, since an NMOS transistor should be used to generate the boost voltage, more layout areas are required.
Accordingly, the present invention is directed to a boost voltage generating circuit for a nonvolatile ferroelectric memory device and method of generating the boost voltage that substantially obviates one or more of problems due to limitations and disadvantages of the related art.
Another object of the present invention is to provide a boost voltage generating circuit for a nonvolatile ferroelectric memory device and method of generating a boost voltage in which an operation is stable when a power source supply voltage region is within a wide power source voltage region.
Another object of the present invention is to provide a boost voltage generating circuit for a nonvolatile ferroelectric memory device and method of generating a boost voltage in which a layout area for generating the boost voltage is reduced, thereby reducing a chip cost.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a boost voltage generating circuit for a nonvolatile ferroelectric memory device includes a supply voltage sensor receiving a voltage boost control signal and determining whether a power source voltage is less than a threshold voltage, a first operation unit receiving an output signal of the supply voltage sensor and the voltage boost control signal and performing a first logic operation, first and second signal output units receiving an output signal of the first operation unit and delaying start and end edges of the voltage boost control signal, thereby outputting first and second boost control signals, and a voltage generating circuit having a ferroelectric capacitor that receives an active signal of an address decoder and the first and second boost control signals when the power source voltage is less than the threshold voltage, thereby generating a boost voltage higher than the power source voltage.
In another aspect of the present invention, a boost voltage generating method for a nonvolatile ferroelectric memory device according to the present invention includes outputting a voltage boost control signal when a chip enable signal is activated in a region where a power source voltage is less than a threshold voltage, delaying start and end edges of the voltage boost control signal to output first and second boost control signals, and inputting the first and second boost control signals into a boost voltage generating circuit having a ferroelectric capacitor to generate a boost voltage higher than the power source voltage.
In a further aspect of the present invention, a boost voltage generating method for a nonvolatile ferroelectric memory device according to the present invention includes outputting a wordline boost control signal of high level having a first width when a chip enable signal is activated and a power source voltage is less than a threshold voltage, delaying only a start edge of the wordline boost control signal to output a first boost control signal, outputting the first boost control signal and at the same time delaying/extending a width equivalent to an end edge of the boost control signal to output a second boost control signal, and inputting an active signal of an address decoder and the first and second boost control signals in a boost voltage generating circuit having a ferroelectric capacitor to generate a boost voltage higher than the power source voltage.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.